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october 2004 dsc-5282/07 1 ?2004 integrated device technology, inc. 128k x 36, 256k x 18, 3.3v synchronous zbt? srams 3.3v i/o, burst counter, flow-through outputs pin description summary it read or write. the idt71v3557/59 contain address, data-in and control signal registers. the outputs are flow-through (no output data register). output enable is the only asynchronous signal and can be used to disable the outputs at any given time. a clock enable ( cen ) pin allows operation of the idt71v3557/59 to be suspended as long as necessary. all synchronous inputs are ignored when ( cen ) is high and the internal device registers will hold their previous values. there are three chip enable pins ( ce 1 , ce 2 , ce 2 ) that allow the user to deselect the device when desired. if any one of these three is not asserted when adv/ ld is low, no new memory operation can be initiated. however, any pending data transfers (reads or writes) will be completed. the data bus will tri-state one cycle after chip is de- selected or a write is initiated. the idt71v3557/59 have an on-chip burst counter. in the burst mode, the idt71v3557/59 can provide four cycles of data for a single address presented to the sram. the order of the burst sequence is defined by the lbo input pin. the lbo pin selects between linear and interleaved burst sequence. the adv/ ld signal is used to load a new external address (adv/ ld = low) or increment the internal burst counter (adv/ ld = high). the idt71v3557/59 srams utilize idt's latest high-performance cmos process and are packaged in a jedec standard 14mm x 20mm 100-pin thin plastic quad flatpack (tqfp) as well as a 119 ball grid array (bga) and a 165 fine pitch ball grid array (fbga). features u u u u u 128k x 36, 256k x 18 memory configurations u u u u u supports high performance system speed - 100 mhz (7.5 ns clock-to-data access) u u u u u zbt tm feature - no dead cycles between write and read cycles u u u u u internally synchronized output buffer enable eliminates the need to control oe oe oe oe oe u u u u u single r/ w w w w w (read/write) control pin u u u u u 4-word burst capability (interleaved or linear) u u u u u individual byte write ( bw bw bw bw bw 1 - bw bw bw bw bw 4 ) control (may tie active) u u u u u three chip enables for simple depth expansion u u u u u 3.3v power supply (5%), 3.3v (5%) i/o supply (v ddq ) u u u u u optional boundary scan jtag interface (ieee 1149.1 complaint) u u u u u packaged in a jedec standard 100-pin plastic thin quad flatpack (tqfp), 119 ball grid array (bga) and 165 fine pitch ball grid array (fbga) description the idt71v3557/59 are 3.3v high-speed 4,718,592-bit (4.5 mega- bit) synchronous srams organized as 128k x 36/256k x 18. they are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. thus they have been given the name zbt tm , or zero bus turnaround. address and control signals are applied to the sram during one clock cycle, and on the next clock cycle the associated data cycle occurs, be a 0 -a 17 address inputs input synchronous ce 1 , ce 2 , ce 2 chip enables input synchronous oe output enable input asynchronous r/ w read/write signal input synchronous cen clock enable input synchronous bw 1 , bw 2 , bw 3 , bw 4 individual byte write selects input synchronous clk clock input n/a adv/ ld advance burst address / load new address input synchronous lbo linear / interleaved burst order input static tms test mode select input synchronous tdi te st data inp ut input synchronous tck te s t c l o c k input n/a tdo te s t da ta o u t p u t output synchronous trst jtag reset (optional) input asynchronous zz sleep mode input synchronous i/o 0 -i/o 31 , i/o p1 -i/o p4 data input / output i/o synchronous v dd , v ddq core power, i/o power supply static v ss ground supply static 5 2 82 tb l 01 idt71v3557s idt71v3559s idt71v3557sa idt71v3559sa
6.42 2 idt71v3557, idt71v3559, 128k x 36, 256k x 18, 3.3v synchronous srams with zbt? feature, 3.3v i/o, burst counter, and flow-through outputs commercial and industrial temperature r anges pin definitions (1) note: 1. all synchronous inputs must meet specified setup and hold times with respect to clk. symbol pin function i/o active description a 0 -a 17 address inputs i n/a synchronous address inputs. the address register is triggered by a combination of the rising edge of clk, adv/ ld low, cen low, and true chip enables. adv/ ld advance / load i n/a adv/ ld is a synchronous input that is used to load the internal registers with new address and control when it is sampled low at the rising edge of clock with the chip selected. when adv/ ld is low with the chip deselected, any burst in progress is terminated. when adv/ ld is sampled high then the internal burst counter is advanced for any burst that was in progress. the external addresses are ignored when adv/ ld is sampled high. r/ w re ad / write i n/a r/ w signal is a synchronous input that identifies whether the current load cycle initiated is a read or write access to the memory array. the data bus activity for the current cycle takes place one clock cycle later. cen clock enable i low sy nchronous clock enable input. when cen is sampled high, all other synchronous inputs, including clock are ignored and outputs remain unchanged. the effect of cen sampled high on the device outputs is as if the low to high clock transition did not occur. for normal operation, cen must be sampled low at rising edge of clock. bw 1 - bw 4 individual byte write enables i low synchronous byte write enables. each 9-bit byte has its own active low byte write enable. on load write cycles (when r/ w and adv/ ld are sampled low) the appropriate byte write signal ( bw 1 - bw 4 ) must be valid. the byte write signal must also be valid on each cycle of a burst write. byte write signals are ignored when r/ w is sampled high. the appropriate byte(s) of data are written into the device one cycle later. bw 1 - bw 4 can all be tied low if always doing write to the entire 36-bit word. ce 1 , ce 2 chip enables i low synchronous active low chip enable. ce 1 and ce 2 are used with ce 2 to enable the idt71v3557/59. ( ce 1 or ce 2 sampled high or ce 2 sampled low) and adv/ ld low at the rising edge of clock, initiates a deselect cycle. the zbt tm has a one cycle deselect, i.e., the data bus will tri-state one clock cycle after deselect is initiated. ce 2 chip enable i high synchronous active high chip enable. ce 2 is used with ce 1 and ce 2 to enable the chip. ce 2 has inverted polarity but otherwise identical to ce 1 and ce 2 . clk clock i n/a this is the clock input to the idt71v3557/59. except for oe , all timing references fo r the device are made with respect to the rising edge of clk. i/o 0 -i/o 31 i/o p1 -i/o p4 data input/output i/o n/a data input/output (i/o) pins. the data input path is registered, triggered by the rising edge of clk. th e data output path is flow-through (no output register). lbo linear burst order i low burst order selection input. when lbo is high the interleaved burst sequence is selected. when lbo is low the linear burst sequence is selected. lbo is a static input, and it must not change during device operation.. oe output enable i low asynchronous output enable. oe must be low to read data from the 71v3557/59. when oe is high the i/o pins are in a high-impedance state. oe d oes not need to be actively controlled for re ad and write cycles. in normal operation, oe can be tied low. tms test mode select i n/a gives input command for tap controller. sampled on rising edge of tdk. this pin has an internal pullup. tdi test data input i n/a serial input of registers placed between tdi and tdo. sampled on rising edge of tck. this pin has an internal pullup. tck test clock i n/a clock input of tap controller. each tap event is clocked. test inputs are captured on rising edge of tck, while test outputs are driven from the falling edge of tck. this pin has an internal pullup. tdo test data output o n/a serial output of registers placed between tdi and tdo. this output is active depending on the state of the tap controller. trst jtag reset (optional) ilow optional asynchronous jtag reset. can be used to reset the tap c ontroller, but not required. jtag reset occurs automatically at power up and also rese ts using tms and tck per ieee 1149.1. if not used trst can be left floating. this pin has an internal pullup. zz sleep mode i high synchronous sleep mode input. zz high will gate the clk internally and power down the idt71v3557/3559 to its lowest power consumption level. data retention is guaranteed in sleep mode. this pin has an internal pulldown. v dd power supply n/a n/a 3.3v core power supply. v ddq po wer sup ply n/a n/a 3.3v i/o sup ply. v ss ground n/a n/a ground. 5282 tbl 02
6.42 idt71v3557, idt71v3559, 128k x 36, 256k x 18, 3.3v synchronous srams with zbt? feature, 3.3v i/o, burst counter, and flow-through outputs commercial and industrial temperature r anges 3 functional block diagram ? 128k x 36 clk dq dq dq address a [0:16] control logic address control di do input r egister 5282 drw 01 clock data i/o [0:31], i/o p[1:4] mux sel gate o e c e 1 ,ce 2 c e 2 r/ w c e n adv/ l d b w x l b o 128k x 36 bit memory array , jtag (sa version) tms tdi tck tdo t r s t (optional)
6.42 4 idt71v3557, idt71v3559, 128k x 36, 256k x 18, 3.3v synchronous srams with zbt? feature, 3.3v i/o, burst counter, and flow-through outputs commercial and industrial temperature r anges functional block diagram ? 256k x 18 recommended dc operating conditions notes: 1. v il (min.) = C1.0v for pulse width less than t cyc /2, once per cycle. 2. v ih (max.) = +6.0v for pulse width less than t cyc /2, once per cycle. clk dq dq dq address a [0:17] control logic address control di do input r egister 5282 drw 01a clock data i/o [0:15], i/o p[1:2] mux sel gate o e c e 1 ,ce 2 c e 2 r/ w c e n adv/ l d b w x l b o 256k x 18 bit memory array , jtag (sa version) tms tdi tck tdo t r s t (optional) symbol parameter min. typ. max. unit v dd core supply voltage 3.135 3.3 3.465 v v ddq i/o supply voltage 3.135 3.3 3.465 v v ss ground 0 0 0 v v ih input high voltage - inputs 2.0 ____ v dd + 0.3 v v ih input high voltage - i/o 2.0 ____ v ddq + 0.3 (2 ) v v il input low voltage -0.3 (1 ) ____ 0.8 v 5282 tbl 04
6.42 idt71v3557, idt71v3559, 128k x 36, 256k x 18, 3.3v synchronous srams with zbt? feature, 3.3v i/o, burst counter, and flow-through outputs commercial and industrial temperature r anges 5 recommended operating temperature and supply voltage pin configuration ? 128k x 36 notes: 1. pins 14, 64, and 66 do not have to be connected directly to v ss as long as the input voltage is < v il . 2. pin 16 does not have to be connected directly to v dd as long as the input voltage is > v ih . 3. pins 83 and 84 are reserved for future 8m and 16m respectively. 4. pin 64 supports zz (sleep mode) for the latest die revisions. top view 100 tqfp 100 99 98 97 96 95 94 93 92 91 90 87 86 85 84 83 82 81 89 88 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 a 6 a 7 c e 1 c e 2 b w 4 b w 3 b w 2 b w 1 c e 2 v d d v s s c lk r / w c e n o e a d v / ld n c (3) n c (3) a 8 a 9 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 n c lb o a 14 a 13 a 12 a 11 a 10 v d d v s s a 0 a 1 a 2 a 3 a 4 a 5 i/o 31 i/o 30 v ddq v ss i/o 29 i/o 28 i/o 27 i/o 26 v ss v ddq i/o 25 i/o 24 v ss v dd i/o 23 i/o 22 v ddq v ss i/o 21 i/o 20 i/o 19 i/o 18 v ss v ddq i/o 17 i/o 16 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 i/o 14 v ddq v ss i/o 13 i/o 12 i/o 11 i/o 10 v ss v ddq i/o 9 i/o 8 v ss v dd i/o 7 i/o 6 v ddq v ss i/o 5 i/o 4 i/o 3 i/o 2 v ss v ddq i/o 1 i/o 0 5282 drw 02 v ss (1) i/o 15 i/o p3 v dd (2) i/o p4 a 15 a 16 i/o p1 v ss/zz (1,4) i/o p2 v ss (1) , n c n c n c grade temperature (1) v ss v dd v ddq commercial 0c to +70c 0v 3.3v5% 3.3v5% industrial -40c to +85c 0v 3.3v5% 3.3v5% 5282 tbl 05 notes: 1. t a is the "instant on" case temperature.
6.42 6 idt71v3557, idt71v3559, 128k x 36, 256k x 18, 3.3v synchronous srams with zbt? feature, 3.3v i/o, burst counter, and flow-through outputs commercial and industrial temperature r anges absolute maximum ratings (1) 100 tqfp capacitance (1) (t a = +25c, f = 1.0mhz) pin configuration ? 256k x 18 notes: 1. pins 14, 64, and 66 do not have to be connected directly to v ss as long as the input voltage is < v il . 2. pin 16 does not have to be connected directly to v dd as long as the input voltage is > v ih . 3. pins 83 and 84 are reserved for future 8m and 16m respectively. 4. pin 64 supports zz (sleep mode) for the latest die revisions. top view 100 tqfp note: 1. this parameter is guaranteed by device characterization, but not production tested. notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v dd terminals only. 3. v ddq terminals only. 4. input terminals only. 5. i/o terminals only. 6. this is a steady-state dc parameter that applies after the power supply has reached its nominal operating value. power sequencing is not necessary; however, the voltage on any input or i/o pin cannot exceed v ddq during power supply ramp up. 7. t a is the "instant on" case temperature. 10099989796959493929190 87868584838281 89 88 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 a 6 a 7 c e 1 c e 2 n c n c b w 2 b w 1 c e 2 v d d v s s c lk r / w c e n o e a d v / ld n c (3) n c (3) a 8 a 9 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 n c lb o a 15 a 14 a 13 a 12 a 11 v d d v s s a 0 a 1 a 2 a 3 a 4 a 5 nc nc v ddq v ss nc i/o p2 i/o 15 i/o 14 v ss v ddq i/o 13 i/o 12 v ss v dd i/o 11 i/o 10 v ddq v ss i/o 9 i/o 8 nc nc v ss v ddq nc nc 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 nc v ddq v ss nc i/o p1 i/o 7 i/o 6 v ss v ddq i/o 5 i/o 4 v ss v dd i/o 3 i/o 2 v ddq v ss i/o 1 i/o 0 nc nc v ss v ddq nc nc 5282 drw 02a v ss (1) nc nc v dd (2) nc a 16 a 17 nc v ss (1) a 10 v ss/zz (1,4) , n c n c n c symbol rating commercial & industrial values unit v te rm (2 ) terminal voltage with respect to gnd -0.5 to +4.6 v v te rm (3,6) terminal voltage with respect to gnd -0.5 to v dd v v te rm (4,6) terminal voltage with respect to gnd -0.5 to v dd +0.5 v v te rm (5,6) terminal voltage with respect to gnd -0.5 to v ddq +0.5 v t a (7) commercial operating temperature -0 to +70 o c industrial operating temperature -40 to +85 o c t bias temperature under bias -55 to +125 o c t stg storage temperature -55 to +125 o c p t power dissipation 2.0 w i out dc output current 50 ma 5282 tbl 06 symbol parameter (1) conditions max. unit c in input capacitance v in = 3dv 5 pf c i/o i/o capacitance v out = 3dv 7 pf 5282 tbl 07 symbol parameter (1) conditions max. unit c in input capacitance v in = 3dv 7 pf c i/o i/o capacitance v out = 3dv 7 pf 5282 tbl 07a 119 bga capacitance (1) (t a = +25c, f = 1.0mhz) symbol parameter (1) conditions max. unit c in input capacitance v in = 3dv tbd pf c i/o i/o capacitance v out = 3dv tbd pf 5282 tb l 07b 119 bga capacitance (1) (t a = +25c, f = 1.0mhz)
6.42 idt71v3557, idt71v3559, 128k x 36, 256k x 18, 3.3v synchronous srams with zbt? feature, 3.3v i/o, burst counter, and flow-through outputs commercial and industrial temperature r anges 7 pin configuration ? 128k x 36, 119 bga pin configuration - 256k x 18, 119 bga top view top view notes: 1. r5 and j5 do not have to be directly connected to v ss as long as the input voltage is < v il. 2. j3 does not have to be directly connected directly to v dd as long as the input voltage is 3 v ih . 3. g4 and a4 are reserved for future 8m and 16m respectively. 4. these pins are nc for the "s" version and the jtag signal listed for the "sa" version. 5. trst is offered as an optional jtag reset if requested in the application. if not needed, can be left floating and will internally be pulled to v dd. 6. pin t7 supports zz (sleep mode) for the latest die revisions. 1234567 a v ddq a 6 a 4 a 8 a 16 v ddq b nc ce 2 a 3 adv/ ld a 9 ce 2 nc c a 7 a 2 v dd a 12 a 15 nc d i/o 16 i/o p3 v ss nc v ss i/o p2 i/o 15 e i/o 17 i/o 18 v ss v ss i/o 13 i/o 14 f v ddq i/o 19 v ss oe v ss i/o 12 v ddq g i/o 20 i/o 21 bw 3 bw 2 i/o 11 i/o 10 h i/o 22 i/o 23 v ss r/ w v ss i/o 9 i/o 8 j v ddq v dd v dd v dd v ddq k i/o 24 i/o 26 v ss clk v ss i/o 6 i/o 7 l i/o 25 i/o 27 bw 4 nc bw 1 i/o 4 i/o 5 m v ddq i/o 28 v ss cen v ss i/o 3 v ddq n i/o 29 i/o 30 v ss a 1 v ss i/o 2 i/o 1 p i/o 31 i/o p4 v ss a 0 v ss i/o 0 i/o p1 r nc a 5 lbo v dd a 13 t nc nc a 10 a 11 a 14 nc nc/zz (6) u v ddq nc/tms (4) nc/tdi (4) nc/tck (4) nc/tdo (4) nc/ trst (4,5) v ddq 5282 drw 13a v ss(1) nc nc(3) ce 1 nc(3) v dd(2) v ss(1) , nc 1234567 a v ddq a 6 a 4 nc(3) a 8 a 16 v ddq b nc ce2 a 3 adv/ ld a 9 ce 2 nc c a 7 a 2 v dd a 13 a 17 nc d i/o 8 nc v ss nc v ss i/o p1 nc e nc i/o 9 v ss v ss nc i/o 7 f v ddq nc v ss oe v ss i/o 6 v ddq g nc i/o 10 bw 2 nc i/o 5 h i/o 11 nc v ss r/ w v ss i/o 4 nc j v ddq v dd v dd v dd v ddq k nc i/o 12 v ss clk v ss nc i/o 3 l i/o 13 nc nc bw 1 i/o 2 nc m v ddq i/o 14 v ss cen v ss nc v ddq n i/o 15 nc v ss a 1 v ss i/o 1 nc p nc i/o p2 v ss a 0 v ss nc i/o 0 r nc a 5 lbo v dd a 12 t nc a 10 a 15 nc a 14 a 11 nc/zz (6) u v ddq nc/tms (4) nc/tdi (4) nc/tck (4) nc/tdo (4) nc/trst (4,5) v ddq 5282 drw 13b nc ss(1) v v ss v ss ce 1 nc(3) v dd(2) v ss(1) , nc
6.42 8 idt71v3557, idt71v3559, 128k x 36, 256k x 18, 3.3v synchronous srams with zbt? feature, 3.3v i/o, burst counter, and flow-through outputs commercial and industrial temperature r anges pin configuration ? 128k x 36, 165 fbga pin configuration - 256k x 18, 165 fbga notes: 1. h1 and n7 do not have to be directly connected to v ss as long as the input voltage is < v il. 2. h2 does not have to be directly connected directly to v dd as long as the input voltage is 3 v ih . 3. a9, b9, b11, a1, r2, and p2 are reserved for future 9m, 18m, 36m, 72m, 144m, and 288m respectively. 4. these pins are nc for the "s" version and the jtag signal listed for the "sa" version. 5. trst is offered as an optional jtag reset if requested in the application. if not needed, can be left floating and will internally be pulled to v dd. 6. pin h11 supports zz (sleep mode) for the latest die revisions. 1234567891011 anc (3) a 7 ce 1 bw 3 bw 2 ce 2 cen adv /ld nc (3) a 8 nc bnc a 6 ce 2 bw 4 bw 1 clk r/ w oe nc (3) a 9 nc (3) ci/o p3 nc v ddq v ss v ss v ss v ss v ss v ddq nc i/o p2 di/o 17 i/o 16 v ddq v dd v ss v ss v ss v dd v ddq i/o 15 i/o 14 ei/o 19 i/o 18 v ddq v dd v ss v ss v ss v dd v ddq i/o 13 i/o 12 fi/o 21 i/o 20 v ddq v dd v ss v ss v ss v dd v ddq i/o 11 i/o 10 gi/o 23 i/o 22 v ddq v dd v ss v ss v ss v dd v ddq i/o 9 i/o 8 hv ss (1) v dd (2) nc v dd v ss v ss v ss v dd nc nc nc/zz (6) ji/o 25 i/o 24 v ddq v dd v ss v ss v ss v dd v ddq i/o 7 i/o 6 ki/o 27 i/o 26 v ddq v dd v ss v ss v ss v dd v ddq i/o 5 i/o 4 li/o 29 i/o 28 v ddq v dd v ss v ss v ss v dd v ddq i/o 3 i/o 2 mi/o 31 i/o 30 v ddq v dd v ss v ss v ss v dd v ddq i/o 1 i/o 0 ni/o p4 nc v ddq v ss nc/ trst (4, 5) nc v ss (1) v ss v ddq nc i/o p1 pncnc (3) a 5 a 2 nc/tdi (4) a 1 nc/tdo (4) a 10 a 13 a 14 nc r lbo nc (3) a 4 a 3 nc/tms (4) a 0 nc/tck (4) a 11 a 12 a 15 a 16 5282 tb l 25 1234567891011 anc (3) a 7 ce 1 bw 2 nc ce 2 cen adv /ld nc (3) a 8 a 10 bnc a 6 ce 2 nc bw 1 clk r/ w oe nc (3) a 9 nc (3) cnc ncv ddq v ss v ss v ss v ss v ss v ddq nc i/o p1 dnc i/o 8 v ddq v dd v ss v ss v ss v dd v ddq nc i/o 7 enc i/o 9 v ddq v dd v ss v ss v ss v dd v ddq nc i/o 6 fnc i/o 10 v ddq v dd v ss v ss v ss v dd v ddq nc i/o 5 gnc i/o 11 v ddq v dd v ss v ss v ss v dd v ddq nc i/o 4 hvss (1) v dd (2) nc v dd v ss v ss v ss v dd nc nc nc/zz (6) ji/o 12 nc v ddq v dd v ss v ss v ss v dd v ddq i/o 3 nc ki/o 13 nc v ddq v dd v ss v ss v ss v dd v ddq i/o 2 nc li/o 14 nc v ddq v dd v ss v ss v ss v dd v ddq i/o 1 nc mi/o 15 nc v ddq v dd v ss v ss v ss v dd v ddq i/o 0 nc ni/o p2 nc v ddq v ss nc / trst (4, 5) nc v ss (1) v ss v ddq nc nc pnc nc (3) a 5 a 2 nc/tdi (4) a 1 nc/tdo (4) a 11 a 14 a 15 nc r lbo nc (3) a 4 a 3 nc/tms (4) a 0 nc/tck (4) a 12 a 13 a 16 a 17 5282 tbl 25a
6.42 idt71v3557, idt71v3559, 128k x 36, 256k x 18, 3.3v synchronous srams with zbt? feature, 3.3v i/o, burst counter, and flow-through outputs commercial and industrial temperature r anges 9 interleaved burst sequence table ( lbo =v dd ) partial truth table for writes (1) synchronous truth table (1) notes: 1. l = v il , h = v ih , x = dont care. 2. when adv/ ld signal is sampled high, the internal burst counter is incremented. the r/ w signal is ignored when the counter is advanced. therefore the nature of the burst cycle (read or write) is determined by the status of the r/ w signal when the first address is loaded at the beginning of the burst cycle. 3. deselect cycle is initiated when either ( ce 1 , or ce 2 is sampled high or ce 2 is sampled low) and adv/ ld is sampled low at rising edge of clock. the data bus will tri-state one cycle after deselect is initiated. 4. when cen is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. the state of all th e internal registers and the i/ os remains unchanged. 5. to select the chip requires ce 1 = l, ce 2 = l and ce 2 = h on these chip enable pins. the chip is deselected if any one of the chip enables is false. 6. device outputs are ensured to be in high-z during device power-up. 7. q - data read from the device, d - data written to the device. notes: 1. l = v il , h = v ih , x = dont care. 2. multiple bytes may be selected during the same cycle. 3. n/a for x18 configuration. note: 1. upon completion of the burst sequence the counter wraps around to its initial state and continues counting. cen r/ w ce 1 , ce 2 (5 ) adv/ ld bw x address used previous cycle current cycle i/o (one cycle later) l l l l valid external x load write d (7 ) l h l l x external x load read q (7 ) l x x h valid internal load write / burst write burst write (advance burst counter) (2 ) d (7 ) l x x h x internal load read / burst read burst read (advance burst counter) (2 ) q (7 ) l x h l x x x deselect or stop (3 ) hiz l x x h x x deselect / noop noop hiz h x x x x x x suspend (4 ) previous value 5282 tbl 08 sequence 1 sequence 2 sequence 3 sequence 4 a1 a0 a1 a0 a1 a0 a1 a0 first address 0 0 0 1 1 0 1 1 second address 0 1 0 0 1 1 1 0 third address 1 0 1 1 0 0 0 1 fourth address (1 ) 11100100 5282 tbl 10 operation r/ w bw 1 bw 2 bw 3 (3 ) bw 4 (3 ) read hxxxx write all bytes lllll write byte 1 (i/o[0:7], i/o p1 ) (2 ) l l hhh write byte 2 (i/o[8:15], i/o p2 ) (2 ) lhlhh write byte 3 (i/o[16:23], i/o p3 ) (2,3) lhhlh write byte 4 (i/o[24:31], i/o p4 ) (2,3) lhhhl no write l hhhh 5282 tbl 09
6.42 10 idt71v3557, idt71v3559, 128k x 36, 256k x 18, 3.3v synchronous srams with zbt? feature, 3.3v i/o, burst counter, and flow-through outputs commercial and industrial temperature r anges functional timing diagram (1) linear burst sequence table ( lbo =v ss ) note: 1. upon completion of the burst sequence the counter wraps around to its initial state and continues counting. notes: 1. this assumes cen , ce 1 , ce 2 and ce 2 are all true. 2. all address, control and data_in are only required to meet set-up and hold time with respect to the rising edge of clock. dat a_out is valid after a clock-to-data delay from the rising edge of clock. n+29 a29 c29 d/q28 address (a 0 -a 16 ) control (r/ w ,adv/ ld , bw x) data i/o [0:31], i/o p[1:4] cycle clock n+30 a30 c30 d/q29 n+31 a31 c31 d/q30 n+32 a32 c32 d/q31 n+33 a33 c33 d/q32 n+34 a34 c34 d/q33 n+35 a35 c35 d/q34 n+36 a36 c36 d/q35 n+37 a37 c37 d/q36 5282 drw 03 (2) (2) (2) , sequence 1 sequence 2 sequence 3 sequence 4 a1 a0 a1 a0 a1 a0 a1 a0 first address 0 0 0 1 1 0 1 1 second address 0 1 1 0 1 1 0 0 third address 1 0 1 1 0 0 0 1 fourth address (1 ) 11000110 5282 tbl 11
6.42 idt71v3557, idt71v3559, 128k x 36, 256k x 18, 3.3v synchronous srams with zbt? feature, 3.3v i/o, burst counter, and flow-through outputs commercial and industrial temperature r anges 11 notes: 1. ce 2 timing transition is identical to ce 1 signal. ce 2 timing transition is identical but inverted to the ce 1 and ce 2 signals. 2. h = high; l = low; x = don't care; z = high impedence. device operation - showing mixed load, burst, deselect and noop cycles (2) cycle address r/ w adv/ ld ce 1 (1 ) cen bw x oe i/o comments na 0 hl llxxd 1 load read n+1 x x h x l x l q 0 burst read n+2 a 1 hl llxlq 0+1 load read n+3 x x l h l x l q 1 deselect or stop n+4 x x h x l x x z noop n+5 a 2 h l l l x x z load read n+6 x x h x l x l q 2 burst read n+7 x x l h l x l q 2+1 deselect or stop n+8 a 3 l l lllxzload write n+9 x x h x l l x d 3 burst write n+10 a 4 l l lllxd 3+1 load write n+11 x x l h l x x d 4 deselect or stop n+12 x x h x l x x z noop n+13 a 5 l l lllxzload write n+14 a 6 hl llxxd 5 load read n+15 a 7 l l llllq 6 load write n+16 x x h x l l x d 7 burst write n+17 a 8 hl llxxd 7+1 load read n+18 x x h x l x l q 8 burst read n+19 a 9 l l llllq 8+1 load write 5282 tbl 12
6.42 12 idt71v3557, idt71v3559, 128k x 36, 256k x 18, 3.3v synchronous srams with zbt? feature, 3.3v i/o, burst counter, and flow-through outputs commercial and industrial temperature r anges read operation (1) burst write operation (1) burst read operation (1) write operation (1) notes: 1. h = high; l = low; x = dont care; z = high impedance. 2. ce 2 timing transition is identical to ce 1 signal. ce 2 timing transition is identical but inverted to the ce 1 and ce 2 signals. notes: 1. h = high; l = low; x = dont care; z = high impedance. 2. ce 2 timing transition is identical to ce 1 signal. ce 2 timing transition is identical but inverted to the ce 1 and ce 2 signals. notes: 1. h = high; l = low; x = dont care; z = high impedance. 2. ce 2 timing transition is identical to ce 1 signal. ce 2 timing transition is identical but inverted to the ce 1 and ce 2 signals. notes: 1. h = high; l = low; x = dont care; z = high impedance. 2. ce 2 timing transition is identical to ce 1 signal. ce 2 timing transition is identical but inverted to the ce 1 and ce 2 signals. cycle address r/ w adv/ ld ce 1 (2 ) cen bw x oe i/o comments na 0 h l l l x x x address and control meet setup n+1 x x x x x x l q 0 contents of address a 0 read out 5282 tbl 13 cycle address r/ w adv/ ld ce 1 (2 ) cen bw x oe i/o comments na 0 h l l l x x x address and control meet setup n+1 x x h x l x l q 0 address a 0 read out, inc. count n+2 x x h x l x l q 0+1 address a 0+1 read out, inc. count n+3 x x h x l x l q 0+2 address a 0+2 read out, inc. count n+4 x x h x l x l q 0+3 address a 0+3 read out, load a 1 n+5 a 1 hl llxlq 0 address a 0 read out, inc. count n+6 x x h x l x l q 1 address a 1 read out, inc. count n+7 a 2 hl llxlq 1+1 address a 1+1 read out, load a 2 5282 tbl 14 cycle address r/ w adv/ ld ce 1 (2 ) cen bw x oe i/o comments na 0 l l l l l x x address and control meet setup n+1 x x x x l x x d 0 write to address a 0 5282 tbl 15 cycle address r/ w adv/ ld ce 1 (2 ) cen bw x oe i/o comments na 0 l l l l l x x address and control meet setup n+1 x x h x l l x d 0 address a 0 write, inc. count n+2 x x h x l l x d 0+1 address a 0+1 write, inc. count n+3 x x h x l l x d 0+2 address a 0+2 write, inc. count n+4 x x h x l l x d 0+3 address a 0+3 write, load a 1 n+5 a 1 l l lllxd 0 address a 0 write, inc. count n+6 x x h x l l x d 1 address a 1 write, inc. count n+7 a 2 l l lllxd 1+1 address a 1+1 write, load a 2 5282 tbl 16
6.42 idt71v3557, idt71v3559, 128k x 36, 256k x 18, 3.3v synchronous srams with zbt? feature, 3.3v i/o, burst counter, and flow-through outputs commercial and industrial temperature r anges 13 read operation with clock enable used (1) write operation with clock enable used (1) notes: 1. h = high; l = low; x = dont care; z = high impedance. 2. ce 2 timing transition is identical to ce 1 signal. ce 2 timing transition is identical but inverted to the ce 1 and ce 2 signals. notes: 1. h = high; l = low; x = dont care; z = high impedance. 2. ce 2 timing transition is identical to ce 1 signal. ce 2 timing transition is identical but inverted to the ce 1 and ce 2 signals. cycle address r/ w adv/ ld ce 1 (2 ) cen bw x oe i/o comments na 0 h l l l x x x addressa 0 and control meet setup n+1 x x x x h x x x clock n+1 ignored n+2 a 1 hl llxlq 0 address a 0 read out, load a 1 n+3 x x x xhxlq 0 clock ignored. data q 0 is on the bus. n+4 x x x xhxlq 0 clock ignored. data q 0 is on the bus. n+5 a 2 hl llxlq 1 address a 1 read out, load a 2 n+6 a 3 hl llxlq 2 address a 2 read out, load a 3 n+7 a 4 hl llxlq 3 address a 3 read out, load a 4 5282 tbl 17 cycle address r/ w adv/ ld ce 1 (2 ) cen bw x oe i/o comments na 0 l l l l l x x address a 0 and control meet setup. n+1 x x x x h x x x clock n+1 ignored. n+2 a 1 l l lllxd 0 write data d 0 , load a 1 . n+3 x x x x h x x x clock ignored. n+4 x x x x h x x x clock ignored. n+5 a 2 l l lllxd 1 write data d 1 , load a 2 n+6 a 3 l l lllxd 2 write data d 2 , load a 3 n+7 a 4 l l lllxd 3 write data d 3 , load a 4 5282 tbl 18
6.42 14 idt71v3557, idt71v3559, 128k x 36, 256k x 18, 3.3v synchronous srams with zbt? feature, 3.3v i/o, burst counter, and flow-through outputs commercial and industrial temperature r anges read operation with chip enable used (1) write operation with chip enable used (1) notes: 1. h = high; l = low; x = dont care; ? = don't know; z = high impedance. 2. ce 2 timing transition is identical to ce 1 signal. ce 2 timing transition is identical but inverted to the ce 1 and ce 2 signals. 3. device outputs are ensured to be in high-z during device power-up. notes: 1. h = high; l = low; x = dont care; ? = don't know; z = high impedance. 2. ce = l is defined as ce 1 = l, ce 2 = l and ce2 = h. ce = h is defined as ce 1 = h, ce 2 = h or ce 2 = l. cycle address r/ w adv/ ld ce 1 (2 ) cen bw x oe i/o (3 ) comments n x x l h l x x ? deselected. n+1 x x l h l x x z deselected. n+2 a 0 h l l l x x z address a 0 and control meet setup. n+3 x x l h l x l q 0 address a 0 read out, deselected. n+4 a 1 h l l l x x z address a 1 and control meet setup. n+5 x x l h l x l q 1 address a 1 read out, deselected. n+6 x x l h l x x z deselected. n+7 a 2 h l l l x x z address a 2 and control meet setup. n+8 x x l h l x l q 2 address a 2 read out, deselected. n+9 x x l h l x x z deselected. 5282 tbl 19 cycle address r/ w adv/ ld ce (2 ) cen bw x oe i/o comments n x x l h l x x ? deselected. n+1 x x l h l x x z deselected. n+2 a 0 l l l l l x z address a 0 and control meet setup n+3 x x l h l x x d 0 data d 0 write in, deselected. n+4 a 1 l l l l l x z address a 1 and control meet setup n+5 x x l h l x x d 1 data d 1 write in, deselected. n+6 x x l h l x x z deselected. n+7 a 2 l l l l l x z address a 2 and control meet setup n+8 x x l h l x x d 2 data d 2 write in, deselected. n+9 x x l h l x x z deselected. 5282 tbl 20
6.42 idt71v3557, idt71v3559, 128k x 36, 256k x 18, 3.3v synchronous srams with zbt? feature, 3.3v i/o, burst counter, and flow-through outputs commercial and industrial temperature r anges 15 dc electrical characteristics over the operating temperature and supply voltage range (v dd = 3.3v +/-5%) figure 2. lumped capacitive load, typical derating figure 1. ac test load ac test loads ac test conditions (v ddq = 3.3v) dc electrical characterics over the operating temperature and supply voltage range (1) (v dd = 3.3v +/-5%) note: 1. the lbo, jtag and zz pins will be internally pulled to v dd and zz will be internally pulled to v ss if it is not actively driven in the application. notes: 1. all values are maximum guaranteed values. 2. at f = f max, inputs are cycling at the maximum frequency of read cycles of 1/t cyc ; f=0 means no input lines are changing. 3. for i/os v hd = v ddq - 0.2v, v ld = 0.2v. for other inputs v hd = v dd - 0.2v, v ld = 0.2v. v ddq /2 50 w i/o z 0 =50 w 5282 drw 04 , 1 2 3 4 20 30 50 100 200 d tcd (typical, ns) capacitance (pf) 80 5 6 5282 drw 05 , symbol parameter test conditions min. max. unit |i l i | input leakage current v dd = max., v in = 0v to v dd ___ 5a |i li | lbo, jtag and zz input leakage current (1 ) v dd = max., v in = 0v to v dd ___ 30 a |i lo | output leakage current v out = 0v to v cc ___ 5a v ol output low voltage i ol = +8ma, v dd = min. ___ 0.4 v v oh output high voltage i oh = -8ma, v dd = min. 2.4 ___ v 5282 tbl 21 symbol parameter test conditions 7.5ns 8ns 8.5ns unit com'l only com'l ind com'l ind i dd operating power supply current device selected, outputs open, adv/ ld = x, v dd = max., v in > v ih or < v il , f = f max (2 ) 275 250 260 225 235 ma i sb1 cmos standby power supply current device deselected, outputs open, v dd = max., v in > v hd or < v ld , f = 0 (2,3) 40 40 45 40 45 ma i sb2 clock running power supply current device deselected, outputs open, v dd = max., v in > v hd or < v ld , f = f max (2,3) 105 10011095105ma i sb3 idle power supply current device selected, outputs open, cen > v ih , v dd = max., v in > v hd or < v ld , f = f max (2,3) 40 40 45 40 45 ma 5282 tbl 2 2 input pulse levels input rise/fall times input timing reference levels output reference levels output load 0 to 3v 2ns 1.5v 1.5v figure 1 5282 tbl 23
6.42 16 idt71v3557, idt71v3559, 128k x 36, 256k x 18, 3.3v synchronous srams with zbt? feature, 3.3v i/o, burst counter, and flow-through outputs commercial and industrial temperature r anges ac electrical characteristics (v dd = 3.3v +/-5%, commercial and industrial temperature ranges) notes: 1. measured as high above 0.6v ddq and low below 0.4v ddq . 2. transition is measured 200mv from steady-state. 3. these parameters are guaranteed with the ac load (figure 1) by device characterization. they are not production tested. 4. to avoid bus contention, the output buffers are designed such that t chz (device turn-off) is about 1ns faster than t clz (device turn-on) at a given temperature and voltage. the specs as shown do not imply bus contention because t clz is a min. parameter that is worse case at totally different test conditions (0 deg. c, 3.465v) than t chz , which is a max. parameter (worse case at 70 deg. c, 3.135v). 5. commercial temperature range only. 7.5ns (5) 8ns 8.5ns symbol parameter min. max. min. max. min. max. unit t cy c clock cycle time 10 ____ 10.5 ____ 11 ____ ns t ch (1 ) clock high pulse width 2.5 ____ 2.7 ____ 3.0 ____ ns t cl (1 ) clock low pulse width 2.5 ____ 2.7 ____ 3.0 ____ ns output parameters t cd clock high to valid data ____ 7.5 ____ 8 ____ 8.5 ns t cd c clock high to data change 2 ____ 2 ____ 2 ____ ns t cl z (2 , 3 ,4 ) clock high to output active 3 ____ 3 ____ 3 ____ ns t chz (2 , 3 ,4 ) clock high to data high-z ____ 5 ____ 5 ____ 5ns t oe output enable access time ____ 5 ____ 5 ____ 5ns t olz (2,3) output enable low to data active 0 ____ 0 ____ 0 ____ ns t ohz (2,3) output enable high to data high-z ____ 5 ____ 5 ____ 5ns set up times t se clock enable setup time 2.0 ____ 2.0 ____ 2.0 ____ ns t sa address setup time 2.0 ____ 2.0 ____ 2.0 ____ ns t sd data in setup time 2.0 ____ 2.0 ____ 2.0 ____ ns t sw read/write (r/ w ) setup time 2.0 ____ 2.0 ____ 2.0 ____ ns t sadv advance/load (adv/ ld ) setup time 2.0 ____ 2.0 ____ 2.0 ____ ns t sc chip enable/select setup time 2.0 ____ 2.0 ____ 2.0 ____ ns t sb byte write enable ( bw x) setup time 2.0 ____ 2.0 ____ 2.0 ____ ns hold times t he clock enable hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t ha address hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t hd data in hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t hw read/write (r/ w ) hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t hadv advance/load (adv/ ld ) hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t hc chip enable/select hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t hb byte write enable ( bw x) hold time 0.5 ____ 0.5 ____ 0.5 ____ ns 5282 tbl 24
6.42 idt71v3557, idt71v3559, 128k x 36, 256k x 18, 3.3v synchronous srams with zbt? feature, 3.3v i/o, burst counter, and flow-through outputs commercial and industrial temperature r anges 17 timing waveform of read cycle (1,2,3,4) notes: 1. q (a 1 ) represents the first output from the external address a 1 . q (a 2 ) represents the first output from the external address a 2 ; q (a 2+1 ) represents the next output data in the burst sequence of the base address a 2 , etc. where address bits a 0 and a 1 are advancing for the four word burst in the sequence defined by the state of the lbo input. 2. ce 2 timing transitions are identical but inverted to the ce 1 and ce 2 signals. for example, when ce 1 and ce 2 are low on this waveform, ce 2 is high. 3. burst ends when new address and control are loaded into the sram by sampling adv/ ld low. 4. r/ w is don't care when the sram is bursting (adv/ ld sampled high). the nature of the burst access (read or write) is fixed by the state of the r/ w signal when new address and control are loaded into the sram. ( c e n high, elim inates current l-h clock edge) q (a 2 +1 ) t c d r ead t c lz t c h z t c d t c d c q (a 2+ 2 ) q (a 1 ) q (a 2 ) q (a 2+ 3 ) q (a 2+ 3 ) q (a 2 ) b urst r ead r ead d a ta o u t (b urst w raps around to initial state) t c d c t h a d v 5282 drw 06 r / w c lk a d v / ld a d d r e s s c e 1 , c e 2 (2) b w 1 - b w 4 o e t h e t s e a 1 a 2 t c h t c l t c y c t s a d v t h w t s w t h a t s a t h c t s c c e n . ,
6.42 18 idt71v3557, idt71v3559, 128k x 36, 256k x 18, 3.3v synchronous srams with zbt? feature, 3.3v i/o, burst counter, and flow-through outputs commercial and industrial temperature r anges timing waveform of write cycles (1,2,3,4,5) notes: 1. d (a 1 ) represents the first input to the external address a 1 . d (a 2 ) represents the first input to the external address a 2 ; d (a 2+1 ) represents the next input data in the burst sequence of the base address a 2 , etc. where address bits a 0 and a 1 are advancing for the four word burst in the sequence defined by the state of the lbo input. 2. ce 2 timing transitions are identical but inverted to the ce 1 and ce 2 signals. for example, when ce 1 and ce 2 are low on this waveform, ce 2 is high. 3. burst ends when new address and control are loaded into the sram by sampling adv/ ld low. 4. r/ w is don't care when the sram is bursting (adv/ ld sampled high). the nature of the burst access (read or write) is fixed by the state of the r/ w signal when new address and control are loaded into the sram. 5. individual byte write signals ( bw x) must be valid on all write and burst-write cycles. a write cycle is initiated when r/ w signal is sampled low. the byte write information comes in one cycle before the actual data is presented to the sram. t h e t s e r / w a 1 a 2 c lk c e n a d v / ld a d d r e s s c e 1 , c e 2 (2) b w 1 - b w 4 o e d a t a in d (a 1 ) d (a 2 ) t h d t s d ( c e n high, elim inates current l-h clock edge) d (a 2+1 ) d (a 2+ 2 ) d (a 2+ 3 ) d (a 2 ) b urst w rite w rite w rite (b urst w raps around to initial state) t h d t s d t c h t c l t c y c t h a d v t s a d v t h w t s w t h a t s a t h c t s c t h b t s b 5282 drw 07 b (a 1 ) b (a 2 ) b (a 2+ 1 ) b (a 2+ 2 ) b (a 2+3 ) b (a 2 ) . ,
6.42 idt71v3557, idt71v3559, 128k x 36, 256k x 18, 3.3v synchronous srams with zbt? feature, 3.3v i/o, burst counter, and flow-through outputs commercial and industrial temperature r anges 19 timing waveform of combined read and write cycles (1,2,3) notes: 1. q (a 1 ) represents the first output from the external address a 1 . d (a 2 ) represents the input data to the sram corresponding to address a 2 . 2. ce 2 timing transitions are identical but inverted to the ce 1 and ce 2 signals. for example, when ce 1 and ce 2 are low on this waveform, ce 2 is high. 3. individual byte write signals ( bw x) must be valid on all write and burst-write cycles. a write cycle is initiated when r/ w signal is sampled low. the byte write information comes in one cycle before the actual data is presented to the sram. t h e t s e r /w a 1 a 2 c lk c e n a d v /ld a d d r e s s c e 1 ,c e 2 (2) b w 1 - b w 4 d a t a o u t q (a 3 ) q (a 1 ) q (a 6 ) q (a 7 ) t c d r ead r ead r ead r ead t c h z 5282 drw 08 w rite t c l z d (a 2 ) d (a 4 ) t c d c d (a 5 ) w rite t c h t c l t c y c t h w t s w t h a t s a a 4 a 3 t h c t s c t s d t h d t h a d v t s a d v a 6 a 7 a 8 a 5 a 9 d a t a in t h b t s b w rite d (a 8 ) w rite b (a 2) b (a 4 ) b (a 5 ) b (a 8 ) o e . ,
6.42 20 idt71v3557, idt71v3559, 128k x 36, 256k x 18, 3.3v synchronous srams with zbt? feature, 3.3v i/o, burst counter, and flow-through outputs commercial and industrial temperature r anges timing waveform of cen operation (1,2,3,4) notes: 1. q (a 1 ) represents the first output from the external address a 1 . d (a 2 ) represents the input data to the sram corresponding to address a 2 . 2. ce 2 timing transitions are identical but inverted to the ce 1 and ce 2 signals. for example, when ce 1 and ce 2 are low on this waveform, ce 2 is high. 3. cen when sampled high on the rising edge of clock will block that l-h transition of the clock from propogating into the sram. the part will behave as if the l-h clock transition did not occur. all internal registers in the sram will retain their previous state. 4. individual byte write signals ( bw x) must be valid on all write and burst-write cycles. a write cycle is initiated when r/ w signal is sampled low. the byte write information comes in one cycle before the actual data is presented to the sram. t h e t s e r / w a 1 a 2 c lk c e n a d v / ld a d d r e s s c e 1 , c e 2 (2) b w 1 - b w 4 o e d a ta o u t q (a 1 ) t c d c q (a 3 ) t c d t c lz q (a 1 ) q (a 4 ) t c d t c d c t c h z d (a 2 ) t s d t h d t c h t c l t c y c t h c t s c a 4 a 5 t h a d v t s a d v t h w t s w t h a t s a a 3 t h b t s b d a t a in 5282 drw 09 b (a 2 ) . ,
6.42 idt71v3557, idt71v3559, 128k x 36, 256k x 18, 3.3v synchronous srams with zbt? feature, 3.3v i/o, burst counter, and flow-through outputs commercial and industrial temperature r anges 21 timing waveform of cs operation (1,2,3,4) notes: 1. q (a 1 ) represents the first output from the external address a 1 . d (a 3 ) represents the input data to the sram corresponding to address a 3 etc. 2. ce 2 timing transitions are identical but inverted to the ce 1 and ce 2 signals. for example, when ce 1 and ce 2 are low on this waveform, ce 2 is high. 3. when either one of the chip enables ( ce 1 , ce2, ce 2 ) is sampled inactive at the rising clock edge, a deselect cycle is initiated. the data-bus tri-states one cycle after the init iation of the deselect cycle. this allows for any pending data transfers (reads or writes) to be completed. 4. individual byte write signals ( bw x) must be valid on all write and burst-write cycles. a write cycle is initiated when r/ w signal is sampled low. the byte write information comes in one cycle before the actual data is presented to the sram. r / w a 1 c lk a d v / l d a d d r e s s c e 1 , c e 2 (2) o e d a t a o u t q (a 1 ) q (a 2 ) q (a 4 ) t c lz q (a 5 ) t c d t c h z t c d c d (a 3 ) t s d t h d t c h t c l t c y c t h c t s c a 5 a 3 t s b d a t a in t h e t s e a 2 t h a t s a a 4 t h w t s w t h b c e n t h a d v t s a d v 5 28 2 drw 10 b w 1 - b w 4 b (a 3 ) . ,
6.42 22 idt71v3557, idt71v3559, 128k x 36, 256k x 18, 3.3v synchronous srams with zbt? feature, 3.3v i/o, burst counter, and flow-through outputs commercial and industrial temperature r anges jtag interface specification (sa version only) tck device inputs (1) / tdi/tms device outputs (2) / tdo trst ( 3 ) t jcd t jdc t jrst t js t jh t jcyc t jrsr t jf t jcl t jr t jch m5282 drw 01 x symbol parameter min. max. units t jcyc jtag clock input period 100 ____ ns t jch jtag clock high 40 ____ ns t jcl jtag clock low 40 ____ ns t jr jtag clock rise time ____ 5 (1 ) ns t jf jtag clock fall time ____ 5 (1 ) ns t jrst jtag reset 50 ____ ns t jrsr jtag reset recovery 50 ____ ns t jcd jtag data output ____ 20 ns t jdc jtag data output hold 0 ____ ns t js jtag setup 25 ____ ns t jh jtag hold 25 ____ ns i5282 tbl 01 register name bit size instruction (ir) 4 bypass (byr) 1 jtag identification (jidr) 32 boundary scan (bsr) note (1) i5282 tbl 03 notes: 1. device inputs = all device inputs except tdi, tms and trst . 2. device outputs = all device outputs except tdo. 3. during power up, trst could be driven low or not be used since the jtag circuit resets automatically. trst is an optional jtag reset. note: 1. the boundary scan descriptive language (bsdl) file for this device is available by contacting your local idt sales representative. jtag ac electrical characteristics (1,2,3,4) scan register sizes notes: 1. guaranteed by design. 2. ac test load (fig. 1) on external output signals. 3. refer to ac test conditions stated earlier in this document. 4. jtag operations occur at one speed (10mhz). the base device may run at any speed specified in this datasheet.
6.42 idt71v3557, idt71v3559, 128k x 36, 256k x 18, 3.3v synchronous srams with zbt? feature, 3.3v i/o, burst counter, and flow-through outputs commercial and industrial temperature r anges 23 notes: 1. device outputs = all device outputs except tdo. 2. device inputs = all device inputs except tdi, tms, and trst . instruction field value description revision number (31:28) 0x2 reserved for version number. idt device id (27:12) 0x209, 0x20b defines idt part number 71v3557sa and 71v3559sa, respectively. idt jedec id (11:1) 0x33 allows unique identification of device vendor as idt. id register indicator bit (bit 0) 1 indicates the presence of an id register. i5282 tbl 02 jtag identification register definitions (sa version only) instruction description opcode extest forces contents of the boundary scan cells onto the device o utputs (1) . places the boundary scan register (bsr) between tdi and tdo. 0000 sample/preload places the boundary scan register (bsr) between tdi and tdo. sample allows data from device inputs (2) and outputs (1) to be captured in the boundary scan cells and shifted serially through tdo. preload allows data to be input serially into the boundary scan cells via the tdi. 0001 device_id loads the jtag id register (jidr) with the vendor id code and places the register between tdi and tdo. 0010 highz places the bypass register (byr) between tdi and tdo. forces all device output drivers to a high-z state. 0011 reserved several combinations are reserved. do not use codes other than those identified for extest, sample/preload, device_id, highz, clamp, validate and bypass instructions. 0100 reserved 0101 reserved 0110 reserved 0111 clamp uses byr. forces contents of the boundary scan cells onto the device outputs. places the bypass register (byr) between tdi and tdo. 1000 reserved same as above. 1001 reserved 1010 reserved 1011 reserved 1100 validate automatically loaded into the instruction register whenever the tap controller passes through the capture-ir state. the lower two bits '01' are mand ated by the ieee std. 1149.1 specification. 1101 reserved same as above. 1110 bypass the bypass instruction is used to truncate the boundary scan register as a single bit in length. 1111 i5282 tbl 04 available jtag instructions
6.42 24 idt71v3557, idt71v3559, 128k x 36, 256k x 18, 3.3v synchronous srams with zbt? feature, 3.3v i/o, burst counter, and flow-through outputs commercial and industrial temperature r anges 100-pin thin quad plastic flatpack (tqfp) package diagram outline
6.42 idt71v3557, idt71v3559, 128k x 36, 256k x 18, 3.3v synchronous srams with zbt? feature, 3.3v i/o, burst counter, and flow-through outputs commercial and industrial temperature r anges 25 119 ball grid array (bga) package diagram outline
6.42 26 idt71v3557, idt71v3559, 128k x 36, 256k x 18, 3.3v synchronous srams with zbt? feature, 3.3v i/o, burst counter, and flow-through outputs commercial and industrial temperature r anges 165 fine pitch ball grid array (fbga) package diagram outline
6.42 idt71v3557, idt71v3559, 128k x 36, 256k x 18, 3.3v synchronous srams with zbt? feature, 3.3v i/o, burst counter, and flow-through outputs commercial and industrial temperature r anges 27 timing waveform of oe operation (1) note: 1. a read operation is assumed to be in progress. ordering information oe data out t ohz t olz t oe q 5282 drw 11 q , 100-pin plastic thin quad flatpack (tqfp) 119 ball grid array (bga) 165 fine pitch ball grid array (fbga) power xx speed xx package pf** bg bq idt xxxx 75* 80 85 access time (t cd ) in tenths of nanoseconds 5282 drw 12 device type idt71v3557 idt71v3559 128kx36 flow-through zbt sram with 3.3v i/o 256kx18 flow-through zbt sram with 3.3v i/o , x process/ temperature range commercial (0c to +70c) industrial (-40c to +85c) blank i *commercial temperature ran g e onl y . ** jtag (sa version) is not available with 100-pin tqfp packa g e xx s sa standard power standard power with jtag interface
6.42 28 idt71v3557, idt71v3559, 128k x 36, 256k x 18, 3.3v synchronous srams with zbt? feature, 3.3v i/o, burst counter, and flow-through outputs commercial and industrial temperature r anges corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 sramhelp@idt.com santa clara, ca 95054 fax: 408-492-8674 800-544-7726 www.idt.com the idt logo is a registered trademark of integrated device technology, inc. datasheet document history 6/30/99 updated to new format 8/23/99 pg. 5, 6 added pin 64 to note 1 and changed pins 38, 42, and 43 to dnu pg. 7 changed u2Cu6 to dnu pg. 15 improved t ch , t cl ; revised t clz pg. 21 added bga package diagrams pg. 23 added datasheet document history 12/31/99 pg. 5, 14, 15, 22 added industrial temperature range offerings 05/02/00 pg. 5,6 insert clarification note to recommended operatingtemperature and absolute max ratings tables pg. 5,6,7 clarify note on tqfp and bga pin configurations; corrected typo in pinout pg. 6 add bga capacitance table pg. 21 add tqfp package diagram outline 05/26/00 add new package offering 13 x 15mm 165 fbga pg. 23 correct 119 bga package diagram outline 07/26/00 pg. 5-8 add zz sleep mode reference note to tqfp, bg119 and bq165 pg. 8 update bq165 pinout pg. 23 update bg119 pinout package diagram dimensions 10/25/00 remove preliminary status pg. 8 add reference note to pin n5 on bq165 pinout, reserved for jtag trst 05/20/02 pg. 1-8,15,22,23,27 added jtag "sa" version functionality and updated zz pin descriptions and notes. 10/15/04 pg. 7 updated pin configuration for the 119 bga - reordered i/o signals on p6, p7 (128k x 36) and p7, n6, l6, k7, h6, g7, f6, e7, d6 (256k x 18). zbt and zerobus turnaround are trademarks of integrated device technology, inc. and the architecture is supported by micron tec hnology and motorola inc.

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